The present invention relates to a method and apparatus for forming laminated thin films or layers, i.e. a multi-layer structure, on a substrate such as a semiconductor wafer or a glass substrate so as to form, for example, a gate electrode of an MOSFET.
In the general method of manufacturing a semiconductor integrated circuit, a film formation on a substrate such as a semiconductor wafer or a glass substrate and a patterned etching of the formed film are carried out repeatedly so as to obtain a desired semiconductor element.
FIGS. 9A and 9B collectively show a conventional method of forming laminated thin films collectively acting as a gate element of an MOSFET on a surface of a semiconductor wafer. As shown in FIG. 9A, an impurity of one conductivity type is diffused through the surface of the wafer W to form a source region 2 and a drain region 4, followed by forming a gate oxide film 6 consisting of, for example, SiO.sub.2, on the wafer surface intermediate between these source and drain regions. As a result, a channel region is formed below the gate oxide film 6 such that the channel region is sandwiched between the source region 2 and the drain region 4. Further, an electrically conductive gate electrode 8 of a multi-layer structure is formed on the gate oxide film 6 so as to prepare an MOS transistor.
In general, the gate electrode 8 is not of a single layer structure. In recent years, the gate electrode 8 is of a two-layer structure in view of, for example, an electrical conductivity of the electrode. In the prior art exemplified in FIGS. 9A and 9B, a polycrystalline silicon (polysilicon) layer 10 doped with phosphorus is directly formed on the gate oxide film 6. Further, a metal silicide layer, e.g., tungsten silicide layer 12, is directly formed on the polysilicon layer 10, as shown in FIG. 9A. Thus, the gate electrode 8 is of a double layer structure consisting of the phosphorus-doped polysilicon layer 10 and the tungsten silicide layer 12.
Recently, a semiconductor integrated circuit is made finer and finer to increase the degree of integration. Naturally, requirements for decreasing a working line width and a gate width are made severer and severer. Also, a film thickness tends to be decreased to meet a requirement for an element of a multi-layer structure. Under the circumstances, each of the independent layers, as well as adjacent layers, collectively forming the multi-layer structure is required to exhibit electrical characteristics equivalent with or superior to those in the prior art in spite of the decreased thickness of each of these layers. The gate electrode 8 of the double-layer structure, which is shown in FIG. 9A, consisting of the phosphorus-doped polysilicon layer 10 and the tungsten silicide layer 12 is intended to meet the above-noted requirements.
It should be noted that a spontaneous oxide film 14 tends to be formed easily on a surface of a silicon-based film, e.g., the phosphorus-doped polysilicon layer 10, upon exposure to the air atmosphere containing water vapor, as shown in FIG. 9B. If the tungsten silicide layer 11 is formed directly on the oxide film 14, the bonding strength between the polysilicon layer 10 and the tungsten silicide layer 12 is impaired. In addition, a sufficient electrical conductivity between these layers 10 and 11 cannot be ensured, leading to deterioration in the electrical characteristics of the gate electrode 8.
In general, the polysilicon layer 10 is formed by a batch system simultaneously handling a large number of wafers in each lot, e.g., 150 wafers. On the other hand, the tungsten silicide layer 12 is formed by one-by-one process. It follows that the many polysilicon layers formed on the wafers by the batch system differ from each other in the exposure time to the air atmosphere and, thus, in the thickness of the spontaneous oxide film formed on the polysilicon layer 10. To overcome this difficulty, a wet etching using, for example, an HF-based vapor is applied to the surface of the polysilicon layer 10 so as to remove the native oxide film 14.
However, even if the native oxide film is removed by a wet etching immediately before formation of the tungsten silicide film 12, it is very difficult to prevent completely the base layer, i.e., polysilicon layer 10, from being adversely affected.
A measure for overcoming the above-noted difficulty is proposed in, for example, Japanese Patent Disclosure (Kokai) No. 2-292866. Specifically, it is proposed to form the phosphorus-doped polysilicon layer 10 within a process chamber, followed by consecutively forming the tungsten silicide layer 12 within the same process chamber.
Where the phosphorus-doped polysilicon layer 10 and the tungsten silicide layer 12 are consecutively formed within the same process chamber as proposed in the prior art noted above, it is certainly possible to prevent a native oxide film from being formed on the surface of the polysilicon layer 10, making it possible to form the electrode 8 exhibiting good electrical characteristics. In this case, however, a new problem is brought about. Specifically, where, for example, 25 wafers in a single lot are successively processed, careful attentions must be paid to a thermal instability on the wall surface of the process chamber or within the wafer-processing apparatus including the process chamber as well as to an instability in terms of the heat emission rate. If an impurity doped-polysilicon layer or the like is formed under this condition, the reproducibility of the formed layer is deteriorated.
Further, if the doped-polysilicon layer 10 and the tungsten silicide layer 12 are formed successively, stress remains in the upper tungsten silicide layer, leading to deterioration in the bonding strength between the tungsten silicide layer and the lower polysilicon layer. What should also be noted is that, an annealing treatment is applied in general at, for example, about 900.degree. C. after formation of the tungsten silicide layer. In this annealing step, oxygen is diffused into the tungsten silicide layer 12 so as to deteriorate the electrical characteristics of the gate electrode 8.
Further, the reaction rate is limited in the reaction for forming a polysilicon layer; whereas, the reactant supply rate is limited in the reaction for forming the tungsten silicide layer. What should be noted is that the conventional shower head structure for introducing reactant gases for forming a film is incapable of coping with the above-noted difference in the rate-limiting type. It follows that the gas stream fails to flow uniformly over the entire substrate surface in the step of forming any of the phosphorus doped-polysilicon layer and the tungsten silicide layer, with the result that the uniformity is impaired in the thickness of the formed film.